1. Field of the Invention
This disclosure relates to digital memory. More particularly, this disclosure provides a high speed stackable memory system and device.
2. Description of the Related Art
As computers and their central processing units ("CPUs") become capable of executing instructions more rapidly, this ability carries with it a need for increased memory size and speed, and also bus size. The need has given rise to much design effort directed toward optimizing current and future memory device designs to provide quick memory response. Commonly recognized current examples of memory devices include dynamic random access memories ("DRAMs"), read only memories ("ROMs"), and static random access memories ("SRAMs"), as well as mechanical and optical devices, such as CD-ROMs.
In performing a typical data read operation, a memory controller (usually the CPU or, in larger systems, a dedicated memory controller) sends a read command to a particular memory chip. This command is propagated to the chip along one or more lines of a command bus. When received by the particular chip, the command causes the chip to locate and direct an output from its internal memory array onto a data bus, as a return data signal intended for the memory controller. The output then propagates along the data bus, which may or may not travel the same route as the command bus. In the example just given, there are three sources of time delay, including the propagation time of a read command from the controller to the chip, the time required for the chip to power its internal registers and to channel the proper output onto the data bus, and the time required for propagation of the output back to the controller.
Similarly, in performing atypical data write operation, the memory controller sends a write command to a particular memory chip along with the data to be written. This command is propagated to the chip along one or more lines of a command bus, while the data is propagated to the chip along one or more lines of a data bus. When received by the particular chip, the command causes the chip to channel the data from the data bus to the specified location of its internal memory array. The data propagating along the data bus may or may not travel the same route as the command propagating along the command bus. In the example just given, there are three sources of time delay, including the propagation time of a write command from the controller to the chip, the time required for propagation of the data from the controller, and the time required for the chip to power its internal registers and to channel the data from the data bus.
Typically, design efforts have focused primarily on improving internal routing and processing of instructions within memory chips. These improvements provide more responsive memory devices by reducing the time delay for a memory chip to channel data between its memory array and the memory bus, and also by allowing a higher frequency or smaller period within which the memory chip can channel data to and from the data bus. Common techniques such as multiplexing or pipelining are used on the memory chips to sequence the channeling of multiple data items onto the data bus. Improvements in memory chips tends to increase the frequency at which the memory chip can channel these data to the memory bus, such that the period related to this frequency is usually smaller than the time delay from the memory array to the data bus, and in an increasing number of computer systems, this period is smaller than the propagation time of a single data item to or from the memory chip to the controller.
These design efforts however, do not address the primary causes of the limitation of the frequency at which data can be channeled onto the data bus. First, the capacitance on the data bus formed by the memory chips themselves and other "loads." Second, the length of the module trace portions, or "stubs," that form part of the data bus, and third, variation in the stub lengths. As a result, many systems are sending data over the data bus at rates far lower than the operating speeds of the CPUs.
The problem of load capacitance and stub length is further explained with reference to FIGS. 1 and 2. FIG. 1 illustrates a data path within a typical memory system 1. The data path includes a memory controller 2, a motherboard 3, memory chips 4, memory modules 5, and a data bus 6. The data bus 6 includes board trace portions 7, module trace portions 8, connectors 9, and termination 10. The memory controller is affixed to the motherboard and is electrically connected to the memory chips via the data bus. The memory chips are affixed to the memory modules. The board trace portion of the data bus is affixed to the motherboard and the module trace portion of the data bus is affixed to the memory modules. The board trace portion has a termination 10. The connectors 9 electrically connect the board trace portions to the module trace portions and mechanically affix the memory modules to the motherboard.
FIG. 2 depicts the electrical equivalent 11 of the typical data path shown in FIG. 1. For ease of reference, each electrical equivalent in FIG. 2 that represents a component shown in FIG. 1 is labeled with the reference numeral of the represented component with the suffix "A". It should be noted that the board trace portion 7A is made up of inductive and capacitive elements which together behave as a transmission line 12 having a set of impedance and transmission delay characteristics. Similarly, each of the module trace portions 8A are made up of inductive and capacitive elements which together behave as transmission line stubs 13, each having its own set of impedance and transmission delay characteristics.
Whenever a board trace such as 7A is broken into individual transmission lines by stubs and loads such as 8A and 4A, the maximum frequency at which data can be channeled on the board trace is reduced. This reduction in caused by interactions of electrical signals propagating along the subs and the board trace, and reflecting off of the stubs, the loads presented by the memory chips and memory controller, and the ends of the board trace. Above a certain frequency, data will not reliably propagate along the board trace. Adding a termination at the end of the board trace such as a termination resistor 10A, can minimize reflections from the end of the board trace, but the termination cannot completely compensate for the negative impact of the stubs and loads.
The frequency that data can be channeled onto the data bus is generally increased as load capacitance and stub lengths are reduced. The load capacitance, however, does not limit the frequency if there are no stubs. That is, if the stub lengths are reduced to zero such that the capacitive loads are connected directly to the board trace, the board trace tends to act like a simple transmission line without limiting the frequency. On the other hand, for data busses with stubs, the stubs will always act to limit the frequency even if the load capacitance is reduced to zero. Therefore, although it is desirable to minimize load capacitance in a system with stubs, reducing the stub length is of primary importance.
FIGS. 3A and 3B depict typical memory modules 5, according to the prior art. Each memory module typically has nine memory chips 4 on a side and a row of connector pins 16 along one edge for making electrical connections with the motherboard mounted connectors 9 (shown in FIG. 1). These memory chips 4 are typically either arranged in one of two fashions. The first is a straight row parallel to the row of connector pins 16 with a short edge of each memory chip facing the connector pins as shown in FIG. 3A. The second is two parallel rows of chips 4 each parallel to the row of connector pins with a long edge facing the row of connector pins 16 as depicted in FIG. 3B. Typically, the size of the standard module and the size of standard memory chips makes a single row of nine memory chip with the long edge facing the connector pins impracticable. A number of data and control trace lines 17 make the electrical connections from the connector pins 16 to the memory chips 4. While the figures show trace line for only one memory chip, it is understood that each of the memory chips would have a number of trace lines connecting it to the connector pins 16. Together, the trace lines 17 make up the board trace portion 8A of FIG. 2.
As can be seen in FIGS. 3A and 3B, the trace lines 17 typically vary in length since the limited space on the module 5 makes it impractical to make all the trace lines the same length. These unequal length trace lines 17 can cause problems in high speed memory systems. This is because data is typically sent simultaneously along multiple trace lines and the unequal length of the trace lines causes the signals to arrive at slightly different times. This is caused by the fact that data propagating along the longest trace lines takes longer to propagate than the data propagating along the shortest trace lines. As a result the memory controller is often required to wait to ensure the data on the longest trace line has arrived. This need to wait limits the overall speed of the memory system.
Together, the loads, stub lengths, and variation in stub lengths significantly slow the operating frequency of memory systems available today. Current memory systems attempt to solve these problems in several ways. One solution is to provide series resistors on the module trace portion of the data bus in order to electrically separate the module trace portion from the board trace portion of the bus. This technique has been successfully used for frequencies of up to 66 MHZ, but has not been very successful at higher frequencies. Another solution is to provide FET switches on the mother board that break the data bus into sections. For example, a switch multiplexor has been used to separate a set of four memory modules into two electrically independent groups of two modules. This approach creates two smaller memory busses, each presenting less inherent capacitance than the original larger bus. Each of these smaller busses however, still have inherent capacitance load on the data bus and thus have limited signal propagation speed.
In order to keep pace with CPU design and the tendency toward increased computer speed, there exists a need for higher frequency memory systems. In particular, there exists a need for a memory system that minimizes the length and variation of stubs on the data bus in order to allow reliable data propagation and to minimize skewing of the data and therefore allow higher frequency of operation.